The present invention relates to a signal processing circuit and more specifically to a signal processing apparatus controlled by a secondary arithmetic processing unit that is controlled by a central processing unit.
The present invention relates to a signal processing system and method and more particularly to a signal processing system including the above-mentioned signal processing circuit and a reset control method in such signal processing system.
Patent literature 1 discloses a reset control system in an information processing apparatus. The information processing apparatus described in patent literature 1 is coupled to a plurality of central processing units. The information processing apparatus receives a reset request and performs a reset process. This reset request belongs to reset requests transmitted from a plurality of the central processing units and is transmitted from the currently operating central processing unit. There may be a reset request transmitted from the central processing unit not operating currently. The information processing apparatus receives such a reset request during a non-processing period after termination of the current process and performs the reset process.
Specifically, the information processing apparatus described in patent literature 1 includes a plurality of flip-flops (FF) and AND circuits corresponding to a plurality of the central processing units. The information processing apparatus sets the value of FF to “1” when the FF belongs to a plurality of FFs and corresponds to the currently operating central processing unit. Values of the other FFs are set to “0s.” Each AND circuit outputs a logical product between an output from each FF and a reset request transmitted from each central processing unit. Accordingly, the reset request is received through the AND circuit only when the reset request is transmitted from the currently operating central processing unit out of a plurality of the central processing units. Reset requests transmitted from the other central processing units are blocked by the AND circuit and are therefore not received. All FFs are set to “1s” to enable reception of the reset requests transmitted by all the central processing units during the non-processing period after termination of the current process and performs the reset process.
Patent literature 1: Japanese Unexamined Patent Application Publication No. Sho 58(1983)-33737